The present invention generally relates to integrated circuits, and particularly to though-substrate vias for three-dimensional (3D) integrated circuits.
Advancements in the area of semiconductor fabrication have enabled the manufacturing of integrated circuits that have a high density of electronic components. A challenge arises where an increase in the number and length of interconnect wirings can cause an increase in circuit resistance-capacitance (RC) delay and power consumption, which can negatively impact circuit performance. Three-dimensional (3D) stacking of integrated circuits can address these challenges. Fabrication of 3D integrated circuits includes at least two silicon wafers stacked vertically. Vertically stacked wafers can reduce interconnect wiring length and increase device density. Deep through-substrate vias (TSVs) are formed to provide interconnections and electrical connectivity between the electronic components of the vertically stacked wafers. Such TSVs may require high aspect ratios, where the via height is large with respect to the via width, to save valuable area on the substrate. Therefore by using TSVs device density can be increased while reducing the total length of interconnection wiring.
However, fabrication techniques such as chemical vapor deposition (CVD) are unable to fill high aspect ratio TSV holes without the risk of pinch-off. Pinch-off refers to build up of deposited material at an opening of a trench or a via hole (e.g., TSV hole). This is a result of the width of a trench or the circumference of a via hole filling twice as fast as their depths. The occurrence of pinch-off may result in the formation of voids, where some volume of a trench or via hole remains unfilled with the deposited material. Void formation can result in an open circuit and if large enough may sever the interconnect structure. Thus, void formation can reduce integrated circuit performance, decrease reliability of interconnects, cause sudden data loss, and reduce the useful life of semiconductor integrated circuit products. In addition, pinch-off can trap undesired process chemicals within a trench or a via hole (e.g., TSV hole).
An alternative technique for fabricating TSVs may include electroplating. Electroplating techniques require a cathode. Generally, the part to be plated can act as the cathode. The cathode can be connected to a negative terminal of an external power supply and thus must be electrically conductive. In order to electroplate a trench or via hole etched in a nonconductive material, a seed layer may be required to act as the cathode. For example, a copper film may be deposited using physical vapor deposition or other known deposition techniques to form the requisite cathode, or seed layer, in preparation for electroplating. When electroplating a trench or via hole an electrical potential is applied to the copper seed layer while the structure is exposed to an electrolyte solution where the desired plating material can plate out onto the cathode. However, the risk of pinch-off remains in via holes fabricated using an electroplating technique because like other deposition techniques the plated material deposits on the sidewalls of the via hole at the same rate it deposits on the bottom of the TSV hole resulting in the circumference of the TSV hole filling twice as fast as its depth.
Accordingly, current fabrication techniques for filling high aspect ratio TSV holes with a conductive material have risks and disadvantages. Despite achievements that have been made in 3D integrated circuit technology to increase device density and reduce the length of interconnection wiring, the challenge of fabricating and filling high aspect ratio TSVs without void formation and chemical entrapment continues to persist.